(1) Field of the Invention
The present invention relates to a thin film transistor arranged in a matrix array and, more particularly, to a thin film transistor which ensures an increased switching rate by using a gate line without forming a separate gate electrode, the enhancement of processing efficiency by simplifying the transistor structure, and an improvement in the driving ability in which the portion of the source line corresponding to a channel width of the thin film transistor has a rounded contour thereby increasing the channel width and the on-current characteristic.
(2) Description of the Related Art
A thin film transistor is a semiconductor element used as an electrical switching means for selective driving of pixel electrodes, e.g., in a liquid crystal display device, and is generally formed as an inverse staggered-type, metal oxide semiconductor transistor. A transistor is formed by which a gate electrode is deposited and patterned on a glass substrate, and an insulating layer, an armophous silicon layer for forming a channel, a source electrode connected to a signal line, and a drain electrode are formed thereon. A plurality of such elements is arranged in a matrix array.
As shown in FIG. 1 illustrating gate and source lines and a drain electrode arranged in a matrix array, the gate line 1 and the source line 2 overlap each other, and the drain electrode 3 is arranged to be separated from the source line 2. The insulating layer and a semiconductor layer 6 are interposed between a gate electrode 1' of the gate line and the source or drain electrode 2' or 3.
As shown in the drawing, the source and drain electrodes 2' and 3 are assigned to a region where a transistor is formed, and a signal outputted from the source electrode 2' is transferred to the drain electrode via a channel layer placed underneath the source electrode 2'. These elements arranged in a matrix array are connected to address lines joining the source or gate electrodes, and conventional elements are formed on these strip-like lines. Therefore, when it comes to manufacture of the thin film transistors according to the prior art the areas to which pixel electrodes are connected to one side of the drain electrodes are limited, and the arranged structure of the matrix is complicated. Such a microscopic arrangement has a slim possibility of success, from a technological point of view.
As shown in FIG. 1, the width of the above channel layer is limited by the width of the source/drain electrodes, and the improvement of the channel width is dependent upon the form of electrode patterns. A primary object of the improvement of the channel width is to apply an on-current satisfactory to the pixel electrodes requiring larger driving current. In order to do so, the improvement of widening the gate electrodes is not preferable to increasing the size of the elements or the whole arrangement, and at the same time, the off-current is increased.
Particularly, these elements assigned in a matrix are connected to address lines joining the source/gate electrodes and conventional elements are formed on these strip-like lines. Therefore, when it comes to the manufacture of the thin film transistors, the areas to which pixel electrodes are connected to one side of the drain electrodes are limited, and the arranged structure of the matrix is complicated. Thus, it is difficult to make an embodiment of such a microscopic arrangement.